Table of Contents
This proposal defines a roadmap towards native vector predication in LLVM, specifically for vector instructions with a mask and/or an explicit vector length. LLVM currently has no target-independent means to model predicated vector instructions for modern SIMD ISAs such as AVX512, ARM SVE, the RISC-V V extension and NEC SX-Aurora. Only some predicated vector operations, such as masked loads and stores, are available through intrinsics [MaskedIR].
The Vector Predication (VP) extensions is a concrete RFC and prototype implementation to achieve native vector predication in LLVM. The VP prototype and all related discussions can be found in the VP patch on Phabricator [VPRFC].
Result: VP usable for IR-level vectorizers (LV, VPlan, RegionVectorizer), potential integration in Clang with builtins.
Result: Backend development based on VP SDNodes.
Result: Optimization of VP intrinsics on par with standard vector instructions.
Result: VP has superseded earlier vector intrinsics.
Result: Native vector predication in IR.
[MaskedIR] | llvm.masked.* intrinsics, https://llvm.org/docs/LangRef.html#masked-vector-load-and-store-intrinsics |
[VPRFC] | RFC: Prototype & Roadmap for vector predication in LLVM, https://reviews.llvm.org/D57504 |